1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof.
2. Related Art
In recent years, there has been an FBC (Floating Body Cell) memory device for a semiconductor memory device expected as a memory alternative to IT (Transistor)-IC (Capacitor) type DRAMs. The FBC memory device has an FET (Field Effect Transistor) including a floating body (hereinafter, also “body”), formed on an SOI (Silicon On Insulator) substrate. The FBC memory device stores data “1” or data “0” based on large and small numbers of majority carriers (holes) accumulated in this body.
In general, a signal amount (a potential difference between the data “1” and the data “0”) of the FBC memory is determined based on a ratio of body-gate capacitance to body-substrate capacitance. When the body-gate capacitance is small, a signal amount becomes large, and when the body-substrate capacitance is large, a signal amount becomes larger. Therefore, to increase the signal amount, it is desired to decrease the body-gate capacitance or to increase the body-substrate capacitance. However, when the body-gate capacitance is small, a word line voltage at data writing needs to be increased. Unless the word line voltage is increased, a charge amount accumulated in the body at the data writing decreases.
Therefore, it is preferable to increase the signal amount by increasing the body-substrate capacitance. In the FBC memory employing an FIN-type MISFET (Metal-Insulator Semiconductor FET), for example, word lines are provided on an upper surface and on both side surfaces of a channel region. Therefore, because the body-gate capacitance of the FIN-type FBC is usually larger than that of a planar type MISFET, it is more preferable to increase the body-substrate capacitance to maintain or increase the signal amount.